Dishing and Erosion effects are well known in copper (Cu) damascene semiconductor manufacturing processes (see FIGS. 1, 2A and 2B). FIG. 1 shows a structure 110 having copper 12 and oxide 11 layers prior to chemical mechanical polishing (CMP). FIG. 2A shows a structure with a Cu dishing condition 120, in which the oxide layer 121 and Cu layer 122 are reduced by respective amounts 123 and 124 below the original height 125 of the top of the oxide layer 121, so that the top of Cu layer 122 is below the top of oxide layer 121. FIG. 2B shows a configuration 130 in a “Cu up” condition, in which the oxide layer 131 and Cu layer 132 are reduced by respective amounts 133 and 134 below the original height 135 of the top of the oxide layer 131, so that the top of Cu layer 132 is above the top of oxide layer 131.
Optimizing these effects during process development can be difficult because they may have clear and opposite interactions with process recipe settings. Thus, it is desirable to have the ability to separate dishing and erosion effects for rapid process development and optimization.
Physical measurements are typically used to confirm dishing and erosion effects during Cu process development. Because these measurement methods are time consuming, it is difficult to gather enough statistics to confirm the stability of the process during process development. Electrical test structures can provide a much larger statistical sample. But because previously developed electrical test structures are essentially “gratings” with fixed line and space across the entire test structure, it can be difficult to separate dishing and erosion effects in such electrical measurements.
The following four documents are hereby incorporated by reference herein in their entireties, as though set forth herein fully: T. Tugbawa et al., “A Mathematical Model of Pattern Dependencies in Cu CMP Processes,” CMP Symposium, Electrochemical Society Meeting, Honolulu, Hi., October 1999; Stine, B. et al. “A Closed-Form Analytic Model for ILD Thickness Variation in CMP Processes,” 1997 Chemical Mechanical Polish for ULSI Multilevel Interconnection Conference (CMP-MIC), p. 266, Santa Clara, February, 1997; Tae Park et al., “Electrical Characterization of Copper Chemical Mechanical Polishing” CMPMIC '99, pp. 184–191, February 1999; and Tae Park et al., “OVERVIEW OF METHODS FOR CHARACTERIZATION OF PATTERN DEPENDENCIES IN COPPER CMP,” Proc. CMP-MIC, pp. 196–205, Santa Clara, Calif., March 2000.
Even if Cu dishing and erosion are well understood during process development, it can be difficult to use that information to analyze the yield and performance variations resulting from Cu dishing and erosion on a particular product design.